1. Field of the Invention
This invention relates to semiconductor devices and more particularly to a process for making field effect transistors on an integrated circuit using a phosphorous doped silicon glass (PSG) reflow process.
2. Description of the Prior Art
The standard phosphorous doped silicon glass (PSG) reflow technique, presently requires the PSG to be defined and etched to provide source and drain contact windows to a device which may be for example a metal oxide semiconductor field effect transistor (MOSFET). It is noted that polycrystalline silicon may be substituted for the metal gate. The main disadvantages of the processing procedure for the standard reflow process where the PSG is defined and etched at each contact window, is that with wet chemical etching, a large amount of ballooning of the PSG may occur at the contact window. With the ballooning of the PSG at the contact window it is very hard to avoid shorting the source and drain diffusion previously made to the gate when metal is deposited in the contact window to provide an electrical interconnection to the source and drain.
A second disadvantage of the standard reflow process is that the phosphorous doped silicon glass reflow is typically done at a high temperature such as 1050.degree. C. If a very heavy phosphorous concentration is used in the doped PSG then the temperature of the PSG reflow may be reduced perhaps as far as 900.degree. C. The high temperature at which PSG reflow occurs tends to drive any PN junction formed prior to the reflow step deeper and thus it is hard to obtain a shallow PN junction necessary for short channel metal oxide semiconductor field effect transistors (MOSFET).
In U.S. Pat. No. 3,887,733 which issued on June 3, 1975 to D. L. Tolliver et al., a doped oxide reflow process is described with hydroxyl ions in contact with the doped oxide while the doped oxide is at a temperature of 1050.degree. C. shortens the time for reflow of about 10 minutes.
In U.S. Pat. No. 4,191,603 which issued on Mar. 4, 1980 to P. L. Garbarino et al., the formation of phosphosilicate glass (PSG) is described as an insulation layer followed by a heat cycle to form the "snapped-back" PSG layer at its edges after etching through the PSG layer and a polysilicon layer. The heat cycle is provided in a nitrogen atmosphere at approximately 1000.degree. C. for approximately one hour.
In U.S. Pat. No. 4,204,894 which issued on May 27, 1980 to T. Komeda et al., a process for fabricating semiconductor devices is described by forming a first insulating layer containing regions of n or p type impurities. A second insulating layer is formed over the first insulating layer wherein the second insulating layer is meltable at low temperature. Portions of the first and second insulating layers are removed so as to selectively expose the semiconductor wafer. A third insulating layer is formed containing regions of n or p type impurities over the surface of said semiconductor wafer. The wafer is heated so as to fluidize, soften or melt the second insulating layer while diffusing the n or p type impurities in the first and third insulating layers into the semiconductor wafer. The third insulating layer is removed by selective etching.
In Japanese Pat. No. 55-75219 which issued on June 6, 1980 to S. Mimura, the source and drain regions in a channel are formed by one high temperature thermal treatment. A phosphosilicate glass (PSG) layer is deposited over a semiconductor wafer having thermal oxide thereon previously etched to form source and drain windows. The PSG layer is etched over and adjacent to the source and drain windows. A second PSG layer is deposited over the first PSG layer and over the source and drain windows. A thermal treatment in nitrogen gas at 1000.degree. C. permits impurities in the second PSG layer to be diffused into the semiconductor wafer forming source and drain regions.
When using PSG which reflows at a temperature between 900.degree. C. to 1050.degree. C., it is desirable to form the source and drain regions by ions implantation after the PSG is reflowed to provide shallower source and drain regions such as for small geometry MOSFET transistors.
Since PSG has a tendency to balloon when contact windows are opened which results in gate to drain shorts when the contact metal is deposited, it is desirable to circumvent the need of opening contact windows through the PSG.
It is further desirable to define PSG several microns outside the thin oxide active device window, i.e., outside the drain gate and source regions.
It is further desirable to provide a fabrication process wherein PSG is reflowed prior to forming the drain and source regions and wherein the source and drain regions are self aligned with coplanar thermal oxide and wherein no contact windows are necessary.
It is further desirable to provide a fabrication process wherein PSG is reflowed prior to forming the drain and source regions and wherein the source and drain regions are self aligned with coplanar oxide and wherein contact windows are provided by a defined layer of silicon nitride.